1. Field of the Invention
This invention relates to digital circuitry and more specifically to data retaining circuit elements.
2. Description of Related Art
Electronic circuit designs are increasingly being optimized for lower power and smaller size requirements for better incorporation into integrated circuit designs. The increase in complexity and gate count within integrated circuits also requires that testability of the circuit be addressed in the designs of integrated circuits. One general methodology of integrated circuit testability is referred to as Level Sensitive Scan Design (LSSD). An LSSD circuit complies with a set of design rules that enhances the observablity and controllability of digital circuit elements so as to enhance testability of integrated circuits.
Data storage elements, which are circuits that retain a logical value, used in LSSD compliant circuits incorporate a design that allows data to be loaded into a storage element through an alternate data input. This alternate input is generally used for circuit test and stimulation. Loading a data storage element with a particular value allows, for example, placing a sequential logic circuit into a desired state. Data storage elements used in LSSD compliant circuits often have alternate data inputs that have a lower bandwidth than the primary data input in order to economize in power and circuit substrate size. This alternate input is sometimes referred to as a “scan input” since it allows a pre-defined state to be “scanned” into the sequential circuit using these data storage elements.
The alternate data input of data storage elements used in LSSD compliant circuits include an alternate data input and an alternate clock input. When the alternate clock input is at a logical low level, the alternate data input is inhibited and no change in storage element state is made. However, the circuit designs of conventional Data storage elements use an alternate data input structure that is somewhat susceptible to electrical noise on the alternate data input. A noise spike of sufficient amplitude on the alternate data input can cause the stored data state of the data storage element to change, even when the alternate clock input is at a logical low level.
A block diagram of a data storage element 100 used in LSSD compliant circuits is shown in FIG. 1. The exemplary data storage element 100 includes two latches, latch L1114 and latch L2118. Latch L1114 has two sets of inputs, a primary input 106 that includes a primary data input D 102 and a primary clock input C 104. The exemplary data storage element 100 further includes an alternate input 112 with an alternate data input I 108 and an alternate clock input A 110. In normal operation of the data storage element 100, data is provided on the primary input D 102 and this data value is selected for storage into latch L1114 upon a transition of the primary clock input C 104 from low to high. The data storage element is also able to select for storage data from the alternate data input 112 by providing a data value on the alternate data input I 108 and then causing this value to be stored into latch L1114 upon a transition of the alternate clock input A 110. Once a data value is stored in L1114, this value is available, after a propagation delay, at the L1 Output 116. The logical value that is present on the L1 Output 116 is stored into latch L2118 upon a transition of clock B 120 from a logical low level to a logical high level. After the L1 Output 116 is stored into latch L2, that logic value is available, after a propagation delay, on the L2 output 122.
An exemplary prior art data storage element circuit 200 for the data storage element 100 is illustrated in FIG. 2. The prior art data storage element circuit 200 has a prior art latch L1 circuit 290, which performs the function of latch L1114 of the data storage element 100, and a prior art latch L2292, which performs the function of latch L2116 of the data storage element 100. Of particular interest in this prior art data storage element circuit 200 is the circuit connected to the alternate input I 108. This circuit consists of a transmission gate formed by transistors TPAC 202 and TNAT 204. Electrical noise typically present on the alternate input I 108 presents a problem in this circuit design when the electrical noise has an amplitude large enough to cause the transmission gate formed by transistors TPAC 202 and TNAT 204 to turn on. In an example where is a logical high or “1” value stored in the prior art Latch L1290 and the alternate clock A 110 is at a logical low value, then the state of the prior art Latch L1290 should not change. However, if there is a negative spike on the alternate clock input 1110, it is possible for the voltage difference between the source and gate of transistor TNAT 204 to be larger than the threshold voltage of that transistor. Transistor TNAT 204 will then turn on and drain the charge holding the logical high value in prior art Latch L1290. A similar scenario is possible with a logical low value is stored in prior art L1290. In that case, the alternate data input I 108 could have a positive electrical noise spike that raises the voltage of the drain of transistor TPAC 202 above VDD by more than the threshold voltage. If the prior art Latch L1290 is storing a logical low value, raising the drain of transistor TPAC 202 above VDD by more than the threshold voltage causes that value to be overwritten with a logical high value.
Alternative prior art designs that address this noise problem have attendant disadvantages. One prior art design to mitigate noise problems is reducing clock speed. Reducing clock speed has the undesirable effect of increasing the time required to perform testing of the circuit. Another prior art design to mitigate noise problems is to use inputs that incorporate a hysteresis so that the threshold level at which a data level change is recognized changes as a function of the level of the stored data. Hysteresis introduces additional circuit complexity and often increases power dissipation. Still another prior art design is to reduce the generation of noise on data lines by using “global wiring” techniques where circuit layouts for individual circuit modules within a circuit are able to extend beyond the physical area of the module itself. Combining global wiring techniques with circuit trace layout rules that prevent long lengths of parallel conductors results in circuits that have reduced noise spikes induced from other circuit traces. Global wiring techniques greatly increase the complexity of a circuit layout and are often difficult to implement and troubleshoot.
What is therefore needed is a data storage element design that includes an alternate data input structure that has increased immunity to noise on the alternate data input line when the alternate clock input is at a logical low level.